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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-22 11:45:49 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-22 11:45:49 -0700 |
| commit | 4486a98fd5928a4e3cdf9cd27c27b7dd821513bb (patch) | |
| tree | 0afd22de8a09ab3995355e3813015c4523bd63fd /passes/cmds/add.cc | |
| parent | cbb85e40e87fbfb1602bb934ed76a97efb9e55c6 (diff) | |
| parent | ec88129a5cf510afc39ea12efa6059bed3eadfc3 (diff) | |
| download | yosys-4486a98fd5928a4e3cdf9cd27c27b7dd821513bb.tar.gz yosys-4486a98fd5928a4e3cdf9cd27c27b7dd821513bb.tar.bz2 yosys-4486a98fd5928a4e3cdf9cd27c27b7dd821513bb.zip | |
Merge remote-tracking branch 'origin/xc7srl' into xc7mux
Diffstat (limited to 'passes/cmds/add.cc')
| -rw-r--r-- | passes/cmds/add.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/cmds/add.cc b/passes/cmds/add.cc index cfccca966..af6f7043d 100644 --- a/passes/cmds/add.cc +++ b/passes/cmds/add.cc @@ -71,7 +71,7 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n RTLIL::Module *mod = design->modules_.at(it.second->type); if (!design->selected_whole_module(mod->name)) continue; - if (mod->get_bool_attribute("\\blackbox")) + if (mod->get_blackbox_attribute()) continue; if (it.second->hasPort(name)) continue; |