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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-08 16:31:59 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-08 16:31:59 -0700 |
| commit | bca3cf684367ac5cf33ac05506d9e604a325bd3f (patch) | |
| tree | b2b29b441c108984719d0b470ec34b779abec511 /misc/yosys.proto | |
| parent | f7c7003a193361285ba59d1315c1e7c26c4c52f1 (diff) | |
| parent | e194e65358058f3a039636d2603cc093f7b75e50 (diff) | |
| download | yosys-bca3cf684367ac5cf33ac05506d9e604a325bd3f.tar.gz yosys-bca3cf684367ac5cf33ac05506d9e604a325bd3f.tar.bz2 yosys-bca3cf684367ac5cf33ac05506d9e604a325bd3f.zip | |
Merge branch 'master' into xaig
Diffstat (limited to 'misc/yosys.proto')
| -rw-r--r-- | misc/yosys.proto | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/misc/yosys.proto b/misc/yosys.proto index 2870176cb..a583e6265 100644 --- a/misc/yosys.proto +++ b/misc/yosys.proto @@ -1,12 +1,12 @@ // // yosys -- Yosys Open SYnthesis Suite -// +// // Copyright (C) 2018 Serge Bazanski <q3k@symbioticeda.com> -// +// // Permission to use, copy, modify, and/or distribute this software for any // purpose with or without fee is hereby granted, provided that the above // copyright notice and this permission notice appear in all copies. -// +// // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -73,7 +73,7 @@ message Module { BitVector bits = 2; } map<string, Port> port = 2; - + // Named cells in this module. message Cell { // Set to true when the name of this cell is automatically created and @@ -129,7 +129,7 @@ message Model { TYPE_FALSE = 6; }; Type type = 1; - + message Port { // Name of port. string portname = 1; @@ -148,7 +148,7 @@ message Model { // Set for AND, NAND. Gate gate = 3; } - + // Set when the node drives given output port(s). message OutPort { // Name of port. |