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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-27 14:02:13 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-27 14:02:13 -0800 |
| commit | e18aeda7ed3b3dbf4700e25c2bc745c93541b3b8 (patch) | |
| tree | f41b454d90ffdff2f08a625cf36932805f3ee8d8 /misc/py_wrap_generator.py | |
| parent | cfb0366a18b0f3cab254636fdf534a3de76af8d5 (diff) | |
| download | yosys-e18aeda7ed3b3dbf4700e25c2bc745c93541b3b8.tar.gz yosys-e18aeda7ed3b3dbf4700e25c2bc745c93541b3b8.tar.bz2 yosys-e18aeda7ed3b3dbf4700e25c2bc745c93541b3b8.zip | |
Fix $lut input ordering -- SigSpec(std::initializer_list<>) is backwards
Just like Verilog...
Diffstat (limited to 'misc/py_wrap_generator.py')
0 files changed, 0 insertions, 0 deletions