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| author | Clifford Wolf <clifford@clifford.at> | 2018-10-20 23:28:09 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-10-20 23:28:09 +0200 |
| commit | f3de732fb4c85c02b64822c0c557a25b158e80ee (patch) | |
| tree | eb537e2edc2e2eebd2cac62b242501650ea56be3 /manual | |
| parent | 11c8a9eb960fdb0a412fabcfbe787cbf5cc3a67d (diff) | |
| parent | 436e3c0a7cbe5a482e14857e4e5a1d02b3464ae8 (diff) | |
| download | yosys-f3de732fb4c85c02b64822c0c557a25b158e80ee.tar.gz yosys-f3de732fb4c85c02b64822c0c557a25b158e80ee.tar.bz2 yosys-f3de732fb4c85c02b64822c0c557a25b158e80ee.zip | |
Merge pull request #674 from rubund/feature/svinterface_at_top
Support for SystemVerilog interfaces as ports in the top level module + test case
Diffstat (limited to 'manual')
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