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| author | Miodrag Milanovic <mmicko@gmail.com> | 2022-01-03 11:57:11 +0100 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2022-01-03 11:57:11 +0100 |
| commit | cb17eeaf5008a87384b3888dc34993928daba918 (patch) | |
| tree | 65de27a2409e30af2bf58501b1ae40c81a9d5913 /manual | |
| parent | cfe940a98b08f1a5d08fb44427db155ba1f18b62 (diff) | |
| download | yosys-cb17eeaf5008a87384b3888dc34993928daba918.tar.gz yosys-cb17eeaf5008a87384b3888dc34993928daba918.tar.bz2 yosys-cb17eeaf5008a87384b3888dc34993928daba918.zip | |
Update manual
Diffstat (limited to 'manual')
| -rw-r--r-- | manual/command-reference-manual.tex | 22 |
1 files changed, 21 insertions, 1 deletions
diff --git a/manual/command-reference-manual.tex b/manual/command-reference-manual.tex index 28d2b6107..2d5f55749 100644 --- a/manual/command-reference-manual.tex +++ b/manual/command-reference-manual.tex @@ -871,6 +871,16 @@ When commands are separated using the ';;;' token, this command will be executed in -purge mode between the commands. \end{lstlisting} +\section{clean\_zerowidth -- clean zero-width connections from the design} +\label{cmd:clean_zerowidth} +\begin{lstlisting}[numbers=left,frame=single] + clean_zerowidth [selection] + +Fixes the selected cells and processes to contain no zero-width connections. +Depending on the cell type, this may be implemented by removing the connection, +widening it to 1-bit, or removing the cell altogether. +\end{lstlisting} + \section{clk2fflogic -- convert clocked FFs to generic \$ff cells} \label{cmd:clk2fflogic} \begin{lstlisting}[numbers=left,frame=single] @@ -3661,6 +3671,11 @@ Additional -D<macro>[=<value>] options may be added after the option indicating the language version (and before file names) to set additional verilog defines. + read {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl} <vhdl-file>.. + +Load the specified VHDL files. (Requires Verific.) + + read {-f|-F} <command-file> Load and execute the specified command file. (Requires Verific.) @@ -7467,7 +7482,7 @@ different compilation units. Additional -D<macro>[=<value>] options may be added after the option indicating the language version (and before file names) to set additional verilog defines. -The macros SYNTHESIS and VERIFIC are defined implicitly. +The macros YOSYS, SYNTHESIS, and VERIFIC are defined implicitly. verific -formal <verilog-file>.. @@ -7475,6 +7490,11 @@ The macros SYNTHESIS and VERIFIC are defined implicitly. Like -sv, but define FORMAL instead of SYNTHESIS. + verific {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl} <vhdl-file>.. + +Load the specified VHDL files into Verific. + + verific {-f|-F} <command-file> Load and execute the specified command file. |