Merge pull request #2358 from whitequark/rename-ilang-to-rtlil

Replace "ILANG" with "RTLIL" everywhere

3 files changed, 14 insertions, 16 deletions

diff --git a/manual/CHAPTER_Overview.tex b/manual/CHAPTER_Overview.tex
index 83cfa5cc4..61d628a9c 100644
--- a/manual/CHAPTER_Overview.tex
+++ b/manual/CHAPTER_Overview.tex
@@ -39,15 +39,15 @@ the RTL Intermediate Language (RTLIL). A more detailed description of this forma
 is given in the next section.
 
 There is also a text representation of the RTLIL data structure that can be
-parsed using the ILANG Frontend.
+parsed using the RTLIL Frontend.
 
 The design data may then be transformed using a series of passes that all
 operate on the RTLIL representation of the design.
 
 Finally the design in RTLIL representation is converted back to text by one
 of the backends, namely the Verilog Backend for generating Verilog netlists
-and the ILANG Backend for writing the RTLIL data in the same format that is
-understood by the ILANG Frontend.
+and the RTLIL Backend for writing the RTLIL data in the same format that is
+understood by the RTLIL Frontend.
 
 With the exception of the AST Frontend, which is called by the high-level HDL
 frontends and can't be called directly by the user, all program modules are
@@ -67,13 +67,13 @@ in different stages of the synthesis.
 		\tikzstyle{data} = [draw, fill=blue!10, ellipse, minimum height=3em, minimum width=7em, node distance=15em]
 		\node[process] (vlog) {Verilog Frontend};
 		\node[process, dashed, fill=green!5] (vhdl) [right of=vlog] {VHDL Frontend};
-		\node[process] (ilang) [right of=vhdl] {ILANG Frontend};
+		\node[process] (ilang) [right of=vhdl] {RTLIL Frontend};
 		\node[data] (ast) [below of=vlog, node distance=5em, xshift=7.5em] {AST};
 		\node[process] (astfe) [below of=ast, node distance=5em] {AST Frontend};
 		\node[data] (rtlil) [below of=astfe, node distance=5em, xshift=7.5em] {RTLIL};
 		\node[process] (pass) [right of=rtlil, node distance=5em, xshift=7.5em] {Passes};
 		\node[process] (vlbe) [below of=rtlil, node distance=7em, xshift=-13em] {Verilog Backend};
-		\node[process] (ilangbe) [below of=rtlil, node distance=7em, xshift=0em] {ILANG Backend};
+		\node[process] (ilangbe) [below of=rtlil, node distance=7em, xshift=0em] {RTLIL Backend};
 		\node[process, dashed, fill=green!5] (otherbe) [below of=rtlil, node distance=7em, xshift=+13em] {Other Backends};
 
 		\draw[-latex] (vlog) -- (ast);
@@ -92,8 +92,7 @@ in different stages of the synthesis.
 
 \section{The RTL Intermediate Language}
 
-All frontends, passes and backends in Yosys operate on a design in RTLIL\footnote{The {\it Language} in {\it RTL Intermediate Language}
-refers to the fact, that RTLIL also has a text representation, usually referred to as {\it Intermediate Language} (ILANG).} representation.
+All frontends, passes and backends in Yosys operate on a design in RTLIL} representation.
 The only exception are the high-level frontends that use the AST representation as an intermediate step before generating RTLIL
 data.
 
@@ -316,7 +315,7 @@ endmodule
 
 In this example there is no data path and therefore the RTLIL::Module generated by
 the frontend only contains a few RTLIL::Wire objects and an RTLIL::Process.
-The RTLIL::Process in ILANG syntax:
+The RTLIL::Process in RTLIL syntax:
 
 \begin{lstlisting}[numbers=left,frame=single,language=rtlil]
 process $proc$ff_with_en_and_async_reset.v:4$1
@@ -362,7 +361,7 @@ also contains an RTLIL::SwitchRule object (lines $3 \dots 12$). Such an object i
 statement as it uses a control signal ({\tt \textbackslash{}reset} in this case) to determine
 which of its cases should be active. The RTLIL::SwitchRule object then contains one RTLIL::CaseRule
 object per case. In this example there is a case\footnote{The
-syntax {\tt 1'1} in the ILANG code specifies a constant with a length of one bit (the first ``1''),
+syntax {\tt 1'1} in the RTLIL code specifies a constant with a length of one bit (the first ``1''),
 and this bit is a one (the second ``1'').} for {\tt \textbackslash{}reset == 1} that causes
 {\tt \$0\textbackslash{}q[0:0]} to be set (lines 4 and 5) and a default case that in turn contains a switch that
 sets {\tt \$0\textbackslash{}q[0:0]} to the value of {\tt \textbackslash{}d} if {\tt
diff --git a/manual/PRESENTATION_Intro.tex b/manual/PRESENTATION_Intro.tex
index 555ec9175..af561d01b 100644
--- a/manual/PRESENTATION_Intro.tex
+++ b/manual/PRESENTATION_Intro.tex
@@ -231,7 +231,7 @@ as Qflow\footnote[frame]{\url{http://opencircuitdesign.com/qflow/}} for ASIC des
 		\node[data] (rtlil) [below of=astfe, node distance=5em, xshift=7.5em] {RTLIL};
 		\node[process] (pass) [right of=rtlil, node distance=5em, xshift=7.5em] {Passes};
 		\node[process] (vlbe) [below of=rtlil, node distance=7em, xshift=-13em] {Verilog Backend};
-		\node[process] (ilangbe) [below of=rtlil, node distance=7em, xshift=0em] {ILANG Backend};
+		\node[process] (ilangbe) [below of=rtlil, node distance=7em, xshift=0em] {RTLIL Backend};
 		\node[process, fill=green!5] (otherbe) [below of=rtlil, node distance=7em, xshift=+13em] {Other Backends};
 
 		\draw[-latex] (vlog) -- (ast);
@@ -484,7 +484,7 @@ Commands for design navigation and investigation:
 \begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
     cd                   # a shortcut for 'select -module <name>'
     ls                   # list modules or objects in modules
-    dump                 # print parts of the design in ilang format
+    dump                 # print parts of the design in RTLIL format
     show                 # generate schematics using graphviz
     select               # modify and view the list of selected objects
 \end{lstlisting}
@@ -502,7 +502,7 @@ Commands for executing scripts or entering interactive mode:
 \begin{frame}[fragile]{\subsecname{} 2/3 \hspace{0pt plus 1 filll} (excerpt)}
 Commands for reading and elaborating the design:
 \begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
-    read_ilang           # read modules from ilang file
+    read_rtlil           # read modules from RTLIL file
     read_verilog         # read modules from Verilog file
     hierarchy            # check, expand and clean up design hierarchy
 \end{lstlisting}
@@ -534,7 +534,7 @@ Commands for writing the results:
     write_blif           # write design to BLIF file
     write_btor           # write design to BTOR file
     write_edif           # write design to EDIF netlist file
-    write_ilang          # write design to ilang file
+    write_rtlil          # write design to RTLIL file
     write_spice          # write design to SPICE netlist file
     write_verilog        # write design to Verilog file
 \end{lstlisting}
diff --git a/manual/PRESENTATION_Prog.tex b/manual/PRESENTATION_Prog.tex
index a9416f82a..3b61361af 100644
--- a/manual/PRESENTATION_Prog.tex
+++ b/manual/PRESENTATION_Prog.tex
@@ -22,7 +22,7 @@
 	\node[data] (rtlil) [below of=astfe, node distance=5em, xshift=7.5em] {RTLIL};
 	\node[process] (pass) [right of=rtlil, node distance=5em, xshift=7.5em] {Passes};
 	\node[process] (vlbe) [below of=rtlil, node distance=7em, xshift=-13em] {Verilog Backend};
-	\node[process] (ilangbe) [below of=rtlil, node distance=7em, xshift=0em] {ILANG Backend};
+	\node[process] (ilangbe) [below of=rtlil, node distance=7em, xshift=0em] {RTLIL Backend};
 	\node[process, fill=green!5] (otherbe) [below of=rtlil, node distance=7em, xshift=+13em] {Other Backends};
 
 	\draw[-latex] (vlog) -- (ast);
@@ -105,8 +105,7 @@ For simplicity we only discuss this version of RTLIL in this presentation.
 
 \begin{frame}{\subsecname}
 \begin{itemize}
-\item The {\tt dump} command prints the design (or parts of it) in ILANG format. This is
-a text representation of RTLIL.
+\item The {\tt dump} command prints the design (or parts of it) in the text representation of RTLIL.
 
 \bigskip
 \item The {\tt show} command visualizes how the components in the design are connected.