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| author | Ahmed Irfan <irfan@levert.(none)> | 2014-11-03 16:18:53 +0100 |
|---|---|---|
| committer | Ahmed Irfan <irfan@levert.(none)> | 2014-11-03 16:18:53 +0100 |
| commit | 3dd316bdc79bb50c2b968808b4917cb8a49a362e (patch) | |
| tree | 4c031b446fdf8f7ce86321bcdb46c462a50cc521 /manual | |
| parent | 6c6cdf736a5371f715a8f7d759e9caf72db5b21e (diff) | |
| download | yosys-3dd316bdc79bb50c2b968808b4917cb8a49a362e.tar.gz yosys-3dd316bdc79bb50c2b968808b4917cb8a49a362e.tar.bz2 yosys-3dd316bdc79bb50c2b968808b4917cb8a49a362e.zip | |
corrections in appnote
Diffstat (limited to 'manual')
| -rw-r--r-- | manual/APPNOTE_012_Verilog_to_BTOR.tex | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/manual/APPNOTE_012_Verilog_to_BTOR.tex b/manual/APPNOTE_012_Verilog_to_BTOR.tex index 7cd73943c..270ccacdd 100644 --- a/manual/APPNOTE_012_Verilog_to_BTOR.tex +++ b/manual/APPNOTE_012_Verilog_to_BTOR.tex @@ -150,7 +150,8 @@ endmodule \begin{figure}[H] \begin{lstlisting}[language=Verilog] -module test(input clk, input rst, output y); +module test(input clk, input rst, output y, + output safety1); reg [2:0] state; output safety1; always @(posedge clk) begin |