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| author | Clifford Wolf <clifford@clifford.at> | 2014-01-19 14:03:40 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-01-19 14:03:40 +0100 |
| commit | 1e67099b77904802880ad7c53d2cac33c6df456f (patch) | |
| tree | 87deccc08f9e4bbbc7d2448852daf68d4ba0b35e /manual | |
| parent | 9a1eb45c7517f224a2516ce235fd53d01d9ef908 (diff) | |
| download | yosys-1e67099b77904802880ad7c53d2cac33c6df456f.tar.gz yosys-1e67099b77904802880ad7c53d2cac33c6df456f.tar.bz2 yosys-1e67099b77904802880ad7c53d2cac33c6df456f.zip | |
Added $assert cell
Diffstat (limited to 'manual')
| -rw-r--r-- | manual/CHAPTER_CellLib.tex | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/manual/CHAPTER_CellLib.tex b/manual/CHAPTER_CellLib.tex index b84e1b30e..b848a2b60 100644 --- a/manual/CHAPTER_CellLib.tex +++ b/manual/CHAPTER_CellLib.tex @@ -418,3 +418,7 @@ from the gate level logic network can be mapped to physical flip-flop cells from pass. The combinatorial logic cells can be mapped to physical cells from a Liberty file via ABC \citeweblink{ABC} using the {\tt abc} pass. +\begin{fixme} +Add information about {\tt \$assert} cells. +\end{fixme} + |