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| author | Clifford Wolf <clifford@clifford.at> | 2016-04-03 17:16:26 +0200 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2016-04-03 17:16:26 +0200 |
| commit | e4e6becba9259a125bfd2788d453f5ac33272d2f (patch) | |
| tree | ab3e2090d2c2cfce7de3d9211be2fd82d361771a /manual/manual.tex | |
| parent | 27e0d29863bcf80520993574415f79b32312c5fb (diff) | |
| parent | 71f9f40fa9e44351f7a9ebabff622c2569689745 (diff) | |
| download | yosys-e4e6becba9259a125bfd2788d453f5ac33272d2f.tar.gz yosys-e4e6becba9259a125bfd2788d453f5ac33272d2f.tar.bz2 yosys-e4e6becba9259a125bfd2788d453f5ac33272d2f.zip | |
Merge pull request #145 from laanwj/master
Add instructions for building manual on Ubuntu
Diffstat (limited to 'manual/manual.tex')
| -rw-r--r-- | manual/manual.tex | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/manual/manual.tex b/manual/manual.tex index ecc7e4c99..67982cbc8 100644 --- a/manual/manual.tex +++ b/manual/manual.tex @@ -151,14 +151,14 @@ availability of a Free and Open Source (FOSS) synthesis tool that can be used as basis for custom tools would be helpful. In the absence of such a tool, the Yosys Open SYnthesis Suite (Yosys) was -developped. This document covers the design and implementation of this tool. +developed. This document covers the design and implementation of this tool. At the moment the main focus of Yosys lies on the high-level aspects of digital synthesis. The pre-existing FOSS logic-synthesis tool ABC is used by Yosys to perform advanced gate-level optimizations. An evaluation of Yosys based on real-world designs is included. It is shown that Yosys can be used as-is to synthesize such designs. The results produced -by Yosys in this tests where successflly verified using formal verification +by Yosys in this tests where successfully verified using formal verification and are comparable in quality to the results produced by a commercial synthesis tool. @@ -172,7 +172,7 @@ University of Technology \cite{BACC}. AIG & And-Inverter-Graph \\ ASIC & Application-Specific Integrated Circuit \\ AST & Abstract Syntax Tree \\ -BDD & Binary Decicion Diagram \\ +BDD & Binary Decision Diagram \\ BLIF & Berkeley Logic Interchange Format \\ EDA & Electronic Design Automation \\ EDIF & Electronic Design Interchange Format \\ |