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| author | Clifford Wolf <clifford@clifford.at> | 2018-09-06 00:18:01 +0200 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2018-09-06 00:18:01 +0200 |
| commit | 12440fcc8f705c117b5f91fae24b7e5c4fbf8560 (patch) | |
| tree | a9955d3cd62399c8c4d5b612dd4717cc6729c2c1 /manual/manual.tex | |
| parent | 5d9d22f66d512d33b2c1a13c4f1a20f944e6acc3 (diff) | |
| download | yosys-12440fcc8f705c117b5f91fae24b7e5c4fbf8560.tar.gz yosys-12440fcc8f705c117b5f91fae24b7e5c4fbf8560.tar.bz2 yosys-12440fcc8f705c117b5f91fae24b7e5c4fbf8560.zip | |
Add $lut support to Verilog back-end
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'manual/manual.tex')
0 files changed, 0 insertions, 0 deletions