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author | Clifford Wolf <clifford@clifford.at> | 2015-07-02 11:14:30 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2015-07-02 11:14:30 +0200 |
commit | 6c84341f22b2758181164e8d5cddd23e3589c90b (patch) | |
tree | 0438ad9becf956e43ebf8665fee89e021b13bcdf /manual/command-reference-manual.tex | |
parent | 053058d78167f7f1ec377fddcee8b648a5ae4138 (diff) | |
download | yosys-6c84341f22b2758181164e8d5cddd23e3589c90b.tar.gz yosys-6c84341f22b2758181164e8d5cddd23e3589c90b.tar.bz2 yosys-6c84341f22b2758181164e8d5cddd23e3589c90b.zip |
Fixed trailing whitespaces
Diffstat (limited to 'manual/command-reference-manual.tex')
-rw-r--r-- | manual/command-reference-manual.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/manual/command-reference-manual.tex b/manual/command-reference-manual.tex index d653f4093..9e542f778 100644 --- a/manual/command-reference-manual.tex +++ b/manual/command-reference-manual.tex @@ -2988,7 +2988,7 @@ from non-zero to zero in the test design. Write the current design to an SPICE netlist file. -big_endian - generate multi-bit ports in MSB first order + generate multi-bit ports in MSB first order (default is LSB first) -neg net_name |