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| author | Larry Doolittle <ldoolitt@recycle.lbl.gov> | 2015-08-14 13:23:01 -0700 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-08-14 23:27:05 +0200 |
| commit | 6c00704a5ef09be46b1f05e2be477e493f37dd38 (patch) | |
| tree | a64fb142c62fd5cd49a9928b5125ea4e133f4471 /manual/command-reference-manual.tex | |
| parent | 022f570563d8b067e9638bc91bbd168f4c5cb817 (diff) | |
| download | yosys-6c00704a5ef09be46b1f05e2be477e493f37dd38.tar.gz yosys-6c00704a5ef09be46b1f05e2be477e493f37dd38.tar.bz2 yosys-6c00704a5ef09be46b1f05e2be477e493f37dd38.zip | |
Another block of spelling fixes
Smaller this time
Diffstat (limited to 'manual/command-reference-manual.tex')
| -rw-r--r-- | manual/command-reference-manual.tex | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/manual/command-reference-manual.tex b/manual/command-reference-manual.tex index 65e418057..dfef1bb05 100644 --- a/manual/command-reference-manual.tex +++ b/manual/command-reference-manual.tex @@ -762,7 +762,7 @@ This pass flattens the design by replacing cells by their implementation. This pass is very similar to the 'techmap' pass. The only difference is that this pass is using the current design as mapping library. -Cells and/or modules with the 'keep_hiearchy' attribute set will not be +Cells and/or modules with the 'keep_hierarchy' attribute set will not be flattened by this command. \end{lstlisting} @@ -3360,7 +3360,7 @@ values referenced above are vectors of this integers. Signal bits that are connected to a constant driver are denoted as string "0" or "1" instead of a number. -For example the following verilog code: +For example the following Verilog code: module test(input x, y); (* keep *) foo #(.P(42), .Q(1337)) |