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| author | Clifford Wolf <clifford@clifford.at> | 2018-05-17 14:10:24 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-05-17 14:10:24 +0200 |
| commit | 177a989e48d13b1b983b28a9c322967548a138ee (patch) | |
| tree | 37f57b505d69160d8efff34d68d8dabd13b7f8c1 /manual/PRESENTATION_Intro | |
| parent | c3be94e967c904d4b7a0591fdaa2d86bc926ec41 (diff) | |
| parent | 4a229e5b953c15ecb31945258e0ca2f7bffe8a3e (diff) | |
| download | yosys-177a989e48d13b1b983b28a9c322967548a138ee.tar.gz yosys-177a989e48d13b1b983b28a9c322967548a138ee.tar.bz2 yosys-177a989e48d13b1b983b28a9c322967548a138ee.zip | |
Merge pull request #550 from jimparis/yosys-upstream
Support SystemVerilog `` extension for macros
Diffstat (limited to 'manual/PRESENTATION_Intro')
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