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authorClifford Wolf <clifford@clifford.at>2014-02-03 16:26:27 +0100
committerClifford Wolf <clifford@clifford.at>2014-02-03 16:26:27 +0100
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@@ -214,6 +214,39 @@ as Qflow\footnote[frame]{\url{http://opencircuitdesign.com/qflow/}} for ASIC des
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+\subsection{Program Components and Data Formats}
+
+\begin{frame}{\subsecname}
+ \begin{center}
+ \begin{tikzpicture}[scale=0.6, every node/.style={transform shape}]
+ \tikzstyle{process} = [draw, fill=green!10, rectangle, minimum height=3em, minimum width=10em, node distance=15em]
+ \tikzstyle{data} = [draw, fill=blue!10, ellipse, minimum height=3em, minimum width=7em, node distance=15em]
+ \node[process] (vlog) {Verilog Frontend};
+ \node[process, dashed, fill=green!5] (vhdl) [right of=vlog] {VHDL Frontend};
+ \node[process] (ilang) [right of=vhdl] {Other Frontends};
+ \node[data] (ast) [below of=vlog, node distance=5em, xshift=7.5em] {AST};
+ \node[process] (astfe) [below of=ast, node distance=5em] {AST Frontend};
+ \node[data] (rtlil) [below of=astfe, node distance=5em, xshift=7.5em] {RTLIL};
+ \node[process] (pass) [right of=rtlil, node distance=5em, xshift=7.5em] {Passes};
+ \node[process] (vlbe) [below of=rtlil, node distance=7em, xshift=-13em] {Verilog Backend};
+ \node[process] (ilangbe) [below of=rtlil, node distance=7em, xshift=0em] {ILANG Backend};
+ \node[process, fill=green!5] (otherbe) [below of=rtlil, node distance=7em, xshift=+13em] {Other Backends};
+
+ \draw[-latex] (vlog) -- (ast);
+ \draw[-latex] (vhdl) -- (ast);
+ \draw[-latex] (ast) -- (astfe);
+ \draw[-latex] (astfe) -- (rtlil);
+ \draw[-latex] (ilang) -- (rtlil);
+ \draw[latex-latex] (rtlil) -- (pass);
+ \draw[-latex] (rtlil) -- (vlbe);
+ \draw[-latex] (rtlil) -- (ilangbe);
+ \draw[-latex] (rtlil) -- (otherbe);
+ \end{tikzpicture}
+ \end{center}
+\end{frame}
+
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+
\subsection{Example Synthesis Script}
\begin{frame}[t]{\subsecname}