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author | Clifford Wolf <clifford@clifford.at> | 2014-02-02 22:26:26 +0100 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-02-02 22:26:26 +0100 |
commit | 982c9da011f51913e3388334aebc407b11647bdc (patch) | |
tree | f2e727a17c14c17750e4f3e08aaa5721e182dcb5 /manual/PRESENTATION_ExSyn/proc_02.v | |
parent | 9d0b69edaafa98c4bb67974415f354a344a5821d (diff) | |
download | yosys-982c9da011f51913e3388334aebc407b11647bdc.tar.gz yosys-982c9da011f51913e3388334aebc407b11647bdc.tar.bz2 yosys-982c9da011f51913e3388334aebc407b11647bdc.zip |
presentation progress
Diffstat (limited to 'manual/PRESENTATION_ExSyn/proc_02.v')
-rw-r--r-- | manual/PRESENTATION_ExSyn/proc_02.v | 16 |
1 files changed, 7 insertions, 9 deletions
diff --git a/manual/PRESENTATION_ExSyn/proc_02.v b/manual/PRESENTATION_ExSyn/proc_02.v index a89c965e4..8e440f6ce 100644 --- a/manual/PRESENTATION_ExSyn/proc_02.v +++ b/manual/PRESENTATION_ExSyn/proc_02.v @@ -1,10 +1,8 @@ -module test(input A, B, C, D, E, - output reg Y); - always @* begin - Y <= A; - if (B) - Y <= C; - if (D) - Y <= E; - end +module test(input D, C, R, RV, + output reg Q); + always @(posedge C, posedge R) + if (R) + Q <= RV; + else + Q <= D; endmodule |