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| author | Clifford Wolf <clifford@clifford.at> | 2014-02-04 16:51:12 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-02-04 16:51:12 +0100 |
| commit | 03d63dd861725ae9a4668a874566603b6b9bc247 (patch) | |
| tree | a155d79656e02157daa5459760a84d162c961b70 /manual/PRESENTATION_ExSyn/abc_01.v | |
| parent | 7a5f378baef95bb1507333d86143662de1b08098 (diff) | |
| download | yosys-03d63dd861725ae9a4668a874566603b6b9bc247.tar.gz yosys-03d63dd861725ae9a4668a874566603b6b9bc247.tar.bz2 yosys-03d63dd861725ae9a4668a874566603b6b9bc247.zip | |
presentation progress
Diffstat (limited to 'manual/PRESENTATION_ExSyn/abc_01.v')
| -rw-r--r-- | manual/PRESENTATION_ExSyn/abc_01.v | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/manual/PRESENTATION_ExSyn/abc_01.v b/manual/PRESENTATION_ExSyn/abc_01.v new file mode 100644 index 000000000..3bc686353 --- /dev/null +++ b/manual/PRESENTATION_ExSyn/abc_01.v @@ -0,0 +1,10 @@ +module test(input clk, a, b, c, + output reg y); + + reg [2:0] q1, q2; + always @(posedge clk) begin + q1 <= { a, b, c }; + q2 <= q1; + y <= ^q2; + end +endmodule |