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author | Clifford Wolf <clifford@clifford.at> | 2014-02-04 16:51:12 +0100 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-02-04 16:51:12 +0100 |
commit | 03d63dd861725ae9a4668a874566603b6b9bc247 (patch) | |
tree | a155d79656e02157daa5459760a84d162c961b70 /manual/PRESENTATION_ExSyn.tex | |
parent | 7a5f378baef95bb1507333d86143662de1b08098 (diff) | |
download | yosys-03d63dd861725ae9a4668a874566603b6b9bc247.tar.gz yosys-03d63dd861725ae9a4668a874566603b6b9bc247.tar.bz2 yosys-03d63dd861725ae9a4668a874566603b6b9bc247.zip |
presentation progress
Diffstat (limited to 'manual/PRESENTATION_ExSyn.tex')
-rw-r--r-- | manual/PRESENTATION_ExSyn.tex | 67 |
1 files changed, 64 insertions, 3 deletions
diff --git a/manual/PRESENTATION_ExSyn.tex b/manual/PRESENTATION_ExSyn.tex index f67b502b2..a889069b4 100644 --- a/manual/PRESENTATION_ExSyn.tex +++ b/manual/PRESENTATION_ExSyn.tex @@ -345,8 +345,41 @@ Finally the {\tt fsm\_map} command can be used to convert the (optimized) {\tt \subsection{The ``techmap'' command} -\begin{frame}{\subsecname} -TBD +\begin{frame}[t]{\subsecname} +\vbox to 0cm{\includegraphics[width=12cm,trim=-18cm 0cm 0cm -34cm]{PRESENTATION_ExSyn/techmap_01.pdf}\vss} +\vskip-0.8cm +The {\tt techmap} command replaces cells with an implementations given as +verilog source. For example implementing a 32 bit adder using 16 bit adders: + +\vbox to 0cm{ +\vskip-0.3cm +\lstinputlisting[basicstyle=\ttfamily\fontsize{6pt}{7pt}\selectfont, language=verilog]{PRESENTATION_ExSyn/techmap_01_map.v} +}\vbox to 0cm{ +\vskip-0.5cm +\lstinputlisting[xleftmargin=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=verilog]{PRESENTATION_ExSyn/techmap_01.v} +\lstinputlisting[xleftmargin=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single]{PRESENTATION_ExSyn/techmap_01.ys} +} +\end{frame} + +\begin{frame}[t]{\subsecname{} -- stdcell mapping} +When {\tt techmap} is used without a map file, it uses a built-in map file +to map all RTL cell types to a generic library of built-in logic gates and registers. + +\bigskip +\begin{block}{The build-in logic gate types are:} +{\tt \$\_INV\_ \$\_AND\_ \$\_OR\_ \$\_XOR\_ \$\_MUX\_} +\end{block} + +\bigskip +\begin{block}{The register types are:} +{\tt \$\_SR\_NN\_ \$\_SR\_NP\_ \$\_SR\_PN\_ \$\_SR\_PP\_ \\ +\$\_DFF\_N\_ \$\_DFF\_P\_ \\ +\$\_DFF\_NN0\_ \$\_DFF\_NN1\_ \$\_DFF\_NP0\_ \$\_DFF\_NP1\_ \\ +\$\_DFF\_PN0\_ \$\_DFF\_PN1\_ \$\_DFF\_PP0\_ \$\_DFF\_PP1\_ \\ +\$\_DFFSR\_NNN\_ \$\_DFFSR\_NNP\_ \$\_DFFSR\_NPN\_ \$\_DFFSR\_NPP\_ \\ +\$\_DFFSR\_PNN\_ \$\_DFFSR\_PNP\_ \$\_DFFSR\_PPN\_ \$\_DFFSR\_PPP\_ \\ +\$\_DLATCH\_N\_ \$\_DLATCH\_P\_} +\end{block} \end{frame} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% @@ -354,7 +387,35 @@ TBD \subsection{The ``abc'' command} \begin{frame}{\subsecname} -TBD +The {\tt abc} command provides an interface to ABC\footnote[frame]{\url{http://www.eecs.berkeley.edu/~alanmi/abc/}}, +an open source tool for low-level logic synthesis. + +\medskip +The {\tt abc} command processes a netlist of internal gate types and can perform: +\begin{itemize} +\item logic minimization (optimization) +\item mapping of logic to standard cell library (liberty format) +\item mapping of logic to k-LUTs (for FPGA synthesis) +\end{itemize} + +\medskip +Optionally {\tt abc} can process registers from one clock domain and perform +sequential optimization (such as register balancing). + +\medskip +ABC is also controlled using scripts. An ABC script can be specified to use +more advanced ABC features. It is also possible to write the design with +{\tt write\_blif} and load the output file into ABC outside of Yosys. +\end{frame} + +\begin{frame}[fragile]{\subsecname{} -- Example} +\begin{columns} +\column[t]{5cm} +\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExSyn/abc_01.v} +\column[t]{5cm} +\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single]{PRESENTATION_ExSyn/abc_01.ys} +\end{columns} +\includegraphics[width=\linewidth,trim=0 0cm 0 0cm]{PRESENTATION_ExSyn/abc_01.pdf} \end{frame} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% |