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authorAhmed Irfan <ahmedirfan1983@gmail.com>2014-09-22 11:35:04 +0200
committerAhmed Irfan <ahmedirfan1983@gmail.com>2014-09-22 11:35:04 +0200
commitd3c67ad9b61f602de1100cd264efd227dcacb417 (patch)
tree88c462c53bdab128cd1edbded42483772f82612a /manual/PRESENTATION_ExOth/axis_test.v
parentb783dbe148e6d246ebd107c0913de2989ab5af48 (diff)
parent13117bb346dd02d2345f716b4403239aebe3d0e2 (diff)
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Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor
added case for memwr cell that is used in muxes (same cell is used more than one time) corrected bug for xnor and logic_not added pmux cell translation Conflicts: backends/btor/btor.cc
Diffstat (limited to 'manual/PRESENTATION_ExOth/axis_test.v')
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diff --git a/manual/PRESENTATION_ExOth/axis_test.v b/manual/PRESENTATION_ExOth/axis_test.v
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+module axis_test(aclk, tready);
+ input aclk, tready;
+ wire aresetn, tvalid;
+ wire [7:0] tdata;
+
+ integer counter = 0;
+ reg aresetn = 0;
+
+ axis_master uut (aclk, aresetn, tvalid, tready, tdata);
+
+ always @(posedge aclk) begin
+ if (aresetn && tready && tvalid) begin
+ if (counter == 0) assert(tdata == 19);
+ if (counter == 1) assert(tdata == 99);
+ if (counter == 2) assert(tdata == 1);
+ if (counter == 3) assert(tdata == 244);
+ if (counter == 4) assert(tdata == 133);
+ if (counter == 5) assert(tdata == 209);
+ if (counter == 6) assert(tdata == 241);
+ if (counter == 7) assert(tdata == 137);
+ if (counter == 8) assert(tdata == 176);
+ if (counter == 9) assert(tdata == 6);
+ counter <= counter + 1;
+ end
+ aresetn <= 1;
+ end
+endmodule