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| author | Clifford Wolf <clifford@clifford.at> | 2014-02-18 19:37:39 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-02-18 19:51:03 +0100 |
| commit | 3d9da919d8ec2f73df77dc1df02b132b12241d8e (patch) | |
| tree | d6b671867161a201c57b2a0d969b6561e68d85ca /manual/PRESENTATION_ExAdv | |
| parent | a71d09421d31b43b6bda6f6958373ec8a409e3c1 (diff) | |
| download | yosys-3d9da919d8ec2f73df77dc1df02b132b12241d8e.tar.gz yosys-3d9da919d8ec2f73df77dc1df02b132b12241d8e.tar.bz2 yosys-3d9da919d8ec2f73df77dc1df02b132b12241d8e.zip | |
Progress in presentation
Diffstat (limited to 'manual/PRESENTATION_ExAdv')
| -rw-r--r-- | manual/PRESENTATION_ExAdv/Makefile | 5 | ||||
| -rw-r--r-- | manual/PRESENTATION_ExAdv/addshift_map.v | 20 | ||||
| -rw-r--r-- | manual/PRESENTATION_ExAdv/addshift_test.v | 5 | ||||
| -rw-r--r-- | manual/PRESENTATION_ExAdv/addshift_test.ys | 6 |
4 files changed, 35 insertions, 1 deletions
diff --git a/manual/PRESENTATION_ExAdv/Makefile b/manual/PRESENTATION_ExAdv/Makefile index 3bbc239a4..2a2858e5f 100644 --- a/manual/PRESENTATION_ExAdv/Makefile +++ b/manual/PRESENTATION_ExAdv/Makefile @@ -1,5 +1,5 @@ -all: select_01.pdf red_or3x1.pdf sym_mul.pdf mymul.pdf mulshift.pdf +all: select_01.pdf red_or3x1.pdf sym_mul.pdf mymul.pdf mulshift.pdf addshift.pdf select_01.pdf: select_01.v select_01.ys ../../yosys select_01.ys @@ -16,3 +16,6 @@ mymul.pdf: mymul_* mulshift.pdf: mulshift_* ../../yosys mulshift_test.ys +addshift.pdf: addshift_* + ../../yosys addshift_test.ys + diff --git a/manual/PRESENTATION_ExAdv/addshift_map.v b/manual/PRESENTATION_ExAdv/addshift_map.v new file mode 100644 index 000000000..b6d91b01b --- /dev/null +++ b/manual/PRESENTATION_ExAdv/addshift_map.v @@ -0,0 +1,20 @@ +module \$add (A, B, Y); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 1; + parameter B_WIDTH = 1; + parameter Y_WIDTH = 1; + + input [A_WIDTH-1:0] A; + input [B_WIDTH-1:0] B; + output [Y_WIDTH-1:0] Y; + + parameter _TECHMAP_BITS_CONNMAP_ = 0; + parameter _TECHMAP_CONNMAP_A_ = 0; + parameter _TECHMAP_CONNMAP_B_ = 0; + + wire _TECHMAP_FAIL_ = A_WIDTH != B_WIDTH || B_WIDTH < Y_WIDTH || + _TECHMAP_CONNMAP_A_ != _TECHMAP_CONNMAP_B_; + + assign Y = A << 1; +endmodule diff --git a/manual/PRESENTATION_ExAdv/addshift_test.v b/manual/PRESENTATION_ExAdv/addshift_test.v new file mode 100644 index 000000000..b53271faa --- /dev/null +++ b/manual/PRESENTATION_ExAdv/addshift_test.v @@ -0,0 +1,5 @@ +module test (A, B, X, Y); +input [7:0] A, B; +output [7:0] X = A + B; +output [7:0] Y = A + A; +endmodule diff --git a/manual/PRESENTATION_ExAdv/addshift_test.ys b/manual/PRESENTATION_ExAdv/addshift_test.ys new file mode 100644 index 000000000..c08f1106a --- /dev/null +++ b/manual/PRESENTATION_ExAdv/addshift_test.ys @@ -0,0 +1,6 @@ +read_verilog addshift_test.v +hierarchy -check -top test + +techmap -map addshift_map.v;; + +show -prefix addshift -format pdf -notitle |