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| author | Clifford Wolf <clifford@clifford.at> | 2019-05-04 09:47:16 +0200 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2019-05-04 09:47:16 +0200 |
| commit | a01386c0e45b4eee5295db440740a1ab271396fe (patch) | |
| tree | c318b5c5f075b5f1f625b183dc512a37fa5343ca /manual/CHAPTER_Verilog.tex | |
| parent | 66d6ca2de2e31d7c0460ae314b61136e42ded8c5 (diff) | |
| download | yosys-a01386c0e45b4eee5295db440740a1ab271396fe.tar.gz yosys-a01386c0e45b4eee5295db440740a1ab271396fe.tar.bz2 yosys-a01386c0e45b4eee5295db440740a1ab271396fe.zip | |
Improve opt_clean handling of unused wires
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'manual/CHAPTER_Verilog.tex')
0 files changed, 0 insertions, 0 deletions