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| author | Clifford Wolf <clifford@clifford.at> | 2015-08-14 10:56:05 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-08-14 10:56:05 +0200 |
| commit | 84bf862f7c58c2b69babf043ff5032f924a3ee4d (patch) | |
| tree | c19a405bc106c2472f1aaa46c36b189db3e5223f /manual/CHAPTER_StateOfTheArt | |
| parent | 80910d13a610886f4430fbd991ada78b2e586ada (diff) | |
| download | yosys-84bf862f7c58c2b69babf043ff5032f924a3ee4d.tar.gz yosys-84bf862f7c58c2b69babf043ff5032f924a3ee4d.tar.bz2 yosys-84bf862f7c58c2b69babf043ff5032f924a3ee4d.zip | |
Spell check (by Larry Doolittle)
Diffstat (limited to 'manual/CHAPTER_StateOfTheArt')
| -rw-r--r-- | manual/CHAPTER_StateOfTheArt/simlib_yosys.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/manual/CHAPTER_StateOfTheArt/simlib_yosys.v b/manual/CHAPTER_StateOfTheArt/simlib_yosys.v index 800cf822d..454c9a83f 100644 --- a/manual/CHAPTER_StateOfTheArt/simlib_yosys.v +++ b/manual/CHAPTER_StateOfTheArt/simlib_yosys.v @@ -19,7 +19,7 @@ * * The internal logic cell simulation library. * - * This verilog library contains simple simulation models for the internal + * This Verilog library contains simple simulation models for the internal * logic cells (_NOT_, _AND_, ...) that are generated by the default technology * mapper (see "stdcells.v" in this directory) and expected by the "abc" pass. * |