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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-16 15:40:53 -0700 |
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| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-16 15:40:53 -0700 |
| commit | 562c9e362487e0aa3a3d250a1a0a8cfcf10cafaa (patch) | |
| tree | d79265bbbdef31af071ece9a5943fa7391a5ce77 /manual/CHAPTER_StateOfTheArt/simlib_hana.v | |
| parent | 958be89c47ae4f11b5de07bc026bc2202e2ebc97 (diff) | |
| download | yosys-562c9e362487e0aa3a3d250a1a0a8cfcf10cafaa.tar.gz yosys-562c9e362487e0aa3a3d250a1a0a8cfcf10cafaa.tar.bz2 yosys-562c9e362487e0aa3a3d250a1a0a8cfcf10cafaa.zip | |
Attach abc_scc_break, abc_carry_{in,out} attr to ports not modules
Diffstat (limited to 'manual/CHAPTER_StateOfTheArt/simlib_hana.v')
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