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| author | Clifford Wolf <clifford@clifford.at> | 2014-01-28 06:55:47 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-01-28 06:55:47 +0100 |
| commit | 2cb47355d4b3e8021a88f68f7a5f33ce46ff51b0 (patch) | |
| tree | 83a3e52f3a46f2db264106798e416da63e7ae743 /manual/CHAPTER_StateOfTheArt/arrays01.v | |
| parent | 842ca2f011a6030faccc690986accb0ca8035ec8 (diff) | |
| download | yosys-2cb47355d4b3e8021a88f68f7a5f33ce46ff51b0.tar.gz yosys-2cb47355d4b3e8021a88f68f7a5f33ce46ff51b0.tar.bz2 yosys-2cb47355d4b3e8021a88f68f7a5f33ce46ff51b0.zip | |
Renamed manual/FILES_* directories
Diffstat (limited to 'manual/CHAPTER_StateOfTheArt/arrays01.v')
| -rw-r--r-- | manual/CHAPTER_StateOfTheArt/arrays01.v | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/manual/CHAPTER_StateOfTheArt/arrays01.v b/manual/CHAPTER_StateOfTheArt/arrays01.v new file mode 100644 index 000000000..bd0eda294 --- /dev/null +++ b/manual/CHAPTER_StateOfTheArt/arrays01.v @@ -0,0 +1,16 @@ +module uut_arrays01(clock, we, addr, wr_data, rd_data); + +input clock, we; +input [3:0] addr, wr_data; +output [3:0] rd_data; +reg [3:0] rd_data; + +reg [3:0] memory [15:0]; + +always @(posedge clock) begin + if (we) + memory[addr] <= wr_data; + rd_data <= memory[addr]; +end + +endmodule |