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authorClifford Wolf <clifford@clifford.at>2014-07-27 01:51:45 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-27 01:51:45 +0200
commit4c4b6021562c598c4510831bd547edaa97d14dac (patch)
tree7d8bde9d617e67431bdb6c51b5e27ea1836fe7a5 /manual/CHAPTER_Prog
parentf9946232adf887e5aa4a48c64f88eaa17e424009 (diff)
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Refactoring: Renamed RTLIL::Module::cells to cells_
Diffstat (limited to 'manual/CHAPTER_Prog')
-rw-r--r--manual/CHAPTER_Prog/stubnets.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/manual/CHAPTER_Prog/stubnets.cc b/manual/CHAPTER_Prog/stubnets.cc
index 9eacfbcb5..a57907435 100644
--- a/manual/CHAPTER_Prog/stubnets.cc
+++ b/manual/CHAPTER_Prog/stubnets.cc
@@ -29,7 +29,7 @@ static void find_stub_nets(RTLIL::Design *design, RTLIL::Module *module, bool re
log("Looking for stub wires in module %s:\n", RTLIL::id2cstr(module->name));
// For all ports on all cells
- for (auto &cell_iter : module->cells)
+ for (auto &cell_iter : module->cells_)
for (auto &conn : cell_iter.second->connections())
{
// Get the signals on the port