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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-20 10:18:01 -0700 |
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| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-20 10:18:01 -0700 |
| commit | f374e0ab7e9a91fa86814b0f750660e92ed16ae6 (patch) | |
| tree | ae525a0ffa0e9588c833cf864f1eea62436afa4f /manual/CHAPTER_Overview.tex | |
| parent | 4e8f0fbce84db96f8cd3d4e1594b30cbc8ec1020 (diff) | |
| parent | 477e566e8d203ec7754c90fc845d7f3f759f2974 (diff) | |
| download | yosys-f374e0ab7e9a91fa86814b0f750660e92ed16ae6.tar.gz yosys-f374e0ab7e9a91fa86814b0f750660e92ed16ae6.tar.bz2 yosys-f374e0ab7e9a91fa86814b0f750660e92ed16ae6.zip | |
Merge remote-tracking branch 'origin/master' into xc7mux
Diffstat (limited to 'manual/CHAPTER_Overview.tex')
| -rw-r--r-- | manual/CHAPTER_Overview.tex | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/manual/CHAPTER_Overview.tex b/manual/CHAPTER_Overview.tex index 2feb0f1cb..1a25c477f 100644 --- a/manual/CHAPTER_Overview.tex +++ b/manual/CHAPTER_Overview.tex @@ -350,6 +350,18 @@ and this bit is a one (the second ``1'').} for {\tt \textbackslash{}reset == 1} sets {\tt \$0\textbackslash{}q[0:0]} to the value of {\tt \textbackslash{}d} if {\tt \textbackslash{}enable} is active (lines $6 \dots 11$). +A case can specify zero or more compare values that will determine whether it matches. Each of the compare values +must be the exact same width as the control signal. When more than one compare value is specified, the case matches +if any of them matches the control signal; when zero compare values are specified, the case always matches (i.e. +it is the default case). + +A switch prioritizes cases from first to last: multiple cases can match, but only the first matched case becomes +active. This normally synthesizes to a priority encoder. The {\tt parallel\_case} attribute allows passes to assume +that no more than one case will match, and {\tt full\_case} attribute allows passes to assume that exactly one +case will match; if these invariants are ever dynamically violated, the behavior is undefined. These attributes +are useful when an invariant invisible to the synthesizer causes the control signal to never take certain +bit patterns. + The lines $13 \dots 16$ then cause {\tt \textbackslash{}q} to be updated whenever there is a positive clock edge on {\tt \textbackslash{}clock} or {\tt \textbackslash{}reset}. |