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| author | whitequark <whitequark@whitequark.org> | 2018-12-20 04:37:28 +0000 |
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| committer | whitequark <whitequark@whitequark.org> | 2018-12-20 04:54:31 +0000 |
| commit | a9ff81dd82d347b5ed867f142e61271aa40d85ee (patch) | |
| tree | 9658152288133e35a7d6f9e27423a568484d6ce8 /manual/CHAPTER_Overview.tex | |
| parent | 3b4290a1b822aca42ceab4a89043329cb060325d (diff) | |
| download | yosys-a9ff81dd82d347b5ed867f142e61271aa40d85ee.tar.gz yosys-a9ff81dd82d347b5ed867f142e61271aa40d85ee.tar.bz2 yosys-a9ff81dd82d347b5ed867f142e61271aa40d85ee.zip | |
manual: document $meminit cell and memory_* passes.
Diffstat (limited to 'manual/CHAPTER_Overview.tex')
| -rw-r--r-- | manual/CHAPTER_Overview.tex | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/manual/CHAPTER_Overview.tex b/manual/CHAPTER_Overview.tex index 964875d57..2feb0f1cb 100644 --- a/manual/CHAPTER_Overview.tex +++ b/manual/CHAPTER_Overview.tex @@ -428,8 +428,8 @@ memory object has the following properties: All read accesses to the memory are transformed to {\tt \$memrd} cells and all write accesses to {\tt \$memwr} cells by the language frontend. These cells consist of independent read- and write-ports -to the memory. The \B{MEMID} parameter on these cells is used to link them together and to the -RTLIL::Memory object they belong to. +to the memory. Memory initialization is transformed to {\tt \$meminit} cells by the language frontend. +The \B{MEMID} parameter on these cells is used to link them together and to the RTLIL::Memory object they belong to. The rationale behind using separate cells for the individual ports versus creating a large multiport memory cell right in the language frontend is that |