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| author | Jim Lawson <ucbjrl@berkeley.edu> | 2019-02-11 12:43:46 -0800 |
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| committer | Jim Lawson <ucbjrl@berkeley.edu> | 2019-02-11 12:43:46 -0800 |
| commit | 311396860b7380e5dc68e66c17d5083d1953fe3f (patch) | |
| tree | c5146a20e59acc342dfe414e1b35fdfe419b9e81 /manual/CHAPTER_Overview.tex | |
| parent | 76696e80041dc5b8f4ba986f4f83d6e7b6854e96 (diff) | |
| parent | e112d2fbf5a31f00ef19e6d05f28fecc1e9c56b9 (diff) | |
| download | yosys-311396860b7380e5dc68e66c17d5083d1953fe3f.tar.gz yosys-311396860b7380e5dc68e66c17d5083d1953fe3f.tar.bz2 yosys-311396860b7380e5dc68e66c17d5083d1953fe3f.zip | |
Merge remote-tracking branch 'upstream/master'
Diffstat (limited to 'manual/CHAPTER_Overview.tex')
| -rw-r--r-- | manual/CHAPTER_Overview.tex | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/manual/CHAPTER_Overview.tex b/manual/CHAPTER_Overview.tex index 964875d57..2feb0f1cb 100644 --- a/manual/CHAPTER_Overview.tex +++ b/manual/CHAPTER_Overview.tex @@ -428,8 +428,8 @@ memory object has the following properties: All read accesses to the memory are transformed to {\tt \$memrd} cells and all write accesses to {\tt \$memwr} cells by the language frontend. These cells consist of independent read- and write-ports -to the memory. The \B{MEMID} parameter on these cells is used to link them together and to the -RTLIL::Memory object they belong to. +to the memory. Memory initialization is transformed to {\tt \$meminit} cells by the language frontend. +The \B{MEMID} parameter on these cells is used to link them together and to the RTLIL::Memory object they belong to. The rationale behind using separate cells for the individual ports versus creating a large multiport memory cell right in the language frontend is that |