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| author | Miodrag Milanović <mmicko@gmail.com> | 2023-01-02 16:07:36 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-01-02 16:07:36 +0100 |
| commit | 257b41cd1fc3f5ce73fd111e7014150f46af833c (patch) | |
| tree | 33aedbe2ca1f0420b182a7dea8606078044902b4 /manual/CHAPTER_Eval/or1200.prj | |
| parent | 3ebc50dee4007f8cca4ffc0e850bc3e86f7641f4 (diff) | |
| parent | f2a4e5f1a077e7980598114adf33951132e60785 (diff) | |
| download | yosys-257b41cd1fc3f5ce73fd111e7014150f46af833c.tar.gz yosys-257b41cd1fc3f5ce73fd111e7014150f46af833c.tar.bz2 yosys-257b41cd1fc3f5ce73fd111e7014150f46af833c.zip | |
Merge pull request #3577 from KrystalDelusion/deprecate_manual
Deprecate manual
Diffstat (limited to 'manual/CHAPTER_Eval/or1200.prj')
| -rw-r--r-- | manual/CHAPTER_Eval/or1200.prj | 37 |
1 files changed, 0 insertions, 37 deletions
diff --git a/manual/CHAPTER_Eval/or1200.prj b/manual/CHAPTER_Eval/or1200.prj deleted file mode 100644 index 9496874e0..000000000 --- a/manual/CHAPTER_Eval/or1200.prj +++ /dev/null @@ -1,37 +0,0 @@ -verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_spram.v" -verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_reg2mem.v" -verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_mem2reg.v" -verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_dpram.v" -verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_amultp2_32x32.v" -verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_wbmux.v" -verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_sprs.v" -verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_rf.v" -verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_operandmuxes.v" -verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_mult_mac.v" -verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_lsu.v" -verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_immu_tlb.v" -verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_if.v" -verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_ic_tag.v" -verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_ic_ram.v" -verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_ic_fsm.v" -verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_genpc.v" -verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_freeze.v" -verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_fpu.v" -verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_except.v" -verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_dmmu_tlb.v" -verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_ctrl.v" -verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_cfgr.v" -verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_alu.v" -verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_wb_biu.v" -verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_tt.v" -verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_sb.v" -verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_qmem_top.v" -verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_pm.v" -verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_pic.v" -verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_immu_top.v" -verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_ic_top.v" -verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_du.v" -verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_dmmu_top.v" -verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_dc_top.v" -verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_cpu.v" -verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_top.v" |