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| author | Clifford Wolf <clifford@clifford.at> | 2018-03-06 15:47:33 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2018-03-06 15:47:33 +0100 |
| commit | dcc4a18d5a4a4827704b81400c8f479da5ecc349 (patch) | |
| tree | 5bbabb5afabd113fef35c551fb8d01ba1cebb233 /manual/APPNOTE_010_Verilog_to_BLIF.tex | |
| parent | 03b49654b1573dfea94f589d24415bf256150165 (diff) | |
| download | yosys-dcc4a18d5a4a4827704b81400c8f479da5ecc349.tar.gz yosys-dcc4a18d5a4a4827704b81400c8f479da5ecc349.tar.bz2 yosys-dcc4a18d5a4a4827704b81400c8f479da5ecc349.zip | |
Update comment about supported SVA in verificsva.cc
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'manual/APPNOTE_010_Verilog_to_BLIF.tex')
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