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| author | Patrick Urban <patrick.urban@web.de> | 2021-10-11 10:19:29 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-11-13 21:53:25 +0100 |
| commit | 4bee908ae87cdff122c21d5f60943731735952fc (patch) | |
| tree | d6417a368b4b19f84273e4fe21b9b69a20e52059 /libs | |
| parent | 3f4ccdf2f5c2d8ee54f594914f201630867ea050 (diff) | |
| download | yosys-4bee908ae87cdff122c21d5f60943731735952fc.tar.gz yosys-4bee908ae87cdff122c21d5f60943731735952fc.tar.bz2 yosys-4bee908ae87cdff122c21d5f60943731735952fc.zip | |
synth_gatemate: Revise block RAM read modes and initialization
* enable mixed read-width / write-width ports in SDP mode
* fix NO_CHANGE and WRITE_THROUGH behavior during read access
* remove redundant zero-initialization
* set A/B_WE bit during map (gatemate_bramopt pass could be removed later)
* differentiate "upper" and "lower" initialization for cascade mode
Diffstat (limited to 'libs')
0 files changed, 0 insertions, 0 deletions