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| author | Miodrag Milanovic <mmicko@gmail.com> | 2021-10-20 10:02:58 +0200 |
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| committer | Miodrag Milanovic <mmicko@gmail.com> | 2021-10-20 10:02:58 +0200 |
| commit | 17269ae59bda6bcf60dbc9ad9d00afc69aa05499 (patch) | |
| tree | 9aac977e351266c61b85867f180d8064c6826af4 /libs/subcircuit/Makefile | |
| parent | 69b2b13ddd98e059f75911fef13718cca23002e3 (diff) | |
| download | yosys-17269ae59bda6bcf60dbc9ad9d00afc69aa05499.tar.gz yosys-17269ae59bda6bcf60dbc9ad9d00afc69aa05499.tar.bz2 yosys-17269ae59bda6bcf60dbc9ad9d00afc69aa05499.zip | |
Option to disable verific VHDL support
Diffstat (limited to 'libs/subcircuit/Makefile')
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