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| author | Clifford Wolf <clifford@clifford.at> | 2016-08-19 18:38:25 +0200 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2016-08-19 18:38:25 +0200 |
| commit | f6629b9c29838879cec6a94d6cb47afc6fbd2db4 (patch) | |
| tree | a75ca899efb7a6d8889fada7a35e298521174457 /kernel | |
| parent | 9b8e06bee177f53c34a9dd6dd907a822f21659be (diff) | |
| download | yosys-f6629b9c29838879cec6a94d6cb47afc6fbd2db4.tar.gz yosys-f6629b9c29838879cec6a94d6cb47afc6fbd2db4.tar.bz2 yosys-f6629b9c29838879cec6a94d6cb47afc6fbd2db4.zip | |
Optimize memory address port width in wreduce and memory_collect, not verilog front-end
Diffstat (limited to 'kernel')
0 files changed, 0 insertions, 0 deletions