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author | Clifford Wolf <clifford@clifford.at> | 2014-12-24 09:51:17 +0100 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-12-24 09:51:17 +0100 |
commit | edb3c9d0c4f0bc3a108ffebc01f02ff4d7354487 (patch) | |
tree | 602fc633af5de89d2d6d1bda480159318f4aa91d /kernel | |
parent | 48ca1ff9ef5bba939348ceeec75ad310afd9fcf8 (diff) | |
download | yosys-edb3c9d0c4f0bc3a108ffebc01f02ff4d7354487.tar.gz yosys-edb3c9d0c4f0bc3a108ffebc01f02ff4d7354487.tar.bz2 yosys-edb3c9d0c4f0bc3a108ffebc01f02ff4d7354487.zip |
Renamed extend() to extend_xx(), changed most users to extend_u0()
Diffstat (limited to 'kernel')
-rw-r--r-- | kernel/rtlil.cc | 15 | ||||
-rw-r--r-- | kernel/rtlil.h | 2 |
2 files changed, 8 insertions, 9 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 5c010dabf..0e8078df6 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -2590,9 +2590,9 @@ void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit) check(); } -void RTLIL::SigSpec::extend(int width, bool is_signed) +void RTLIL::SigSpec::extend_xx(int width, bool is_signed) { - cover("kernel.rtlil.sigspec.extend"); + cover("kernel.rtlil.sigspec.extend_xx"); pack(); @@ -2600,10 +2600,9 @@ void RTLIL::SigSpec::extend(int width, bool is_signed) remove(width, width_ - width); if (width_ < width) { - RTLIL::SigSpec padding = width_ > 0 ? extract(width_ - 1, 1) : RTLIL::SigSpec(RTLIL::State::S0); - if (!is_signed && padding != RTLIL::SigSpec(RTLIL::State::Sx) && padding != RTLIL::SigSpec(RTLIL::State::Sz) && - padding != RTLIL::SigSpec(RTLIL::State::Sa) && padding != RTLIL::SigSpec(RTLIL::State::Sm)) - padding = RTLIL::SigSpec(RTLIL::State::S0); + RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::S0; + if (!is_signed && (padding == RTLIL::State::S1 || padding.wire)) + padding = RTLIL::State::S0; while (width_ < width) append(padding); } @@ -2619,9 +2618,9 @@ void RTLIL::SigSpec::extend_u0(int width, bool is_signed) remove(width, width_ - width); if (width_ < width) { - RTLIL::SigSpec padding = width_ > 0 ? extract(width_ - 1, 1) : RTLIL::SigSpec(RTLIL::State::S0); + RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::S0; if (!is_signed) - padding = RTLIL::SigSpec(RTLIL::State::S0); + padding = RTLIL::State::S0; while (width_ < width) append(padding); } diff --git a/kernel/rtlil.h b/kernel/rtlil.h index efb8e833a..99831244e 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -1057,7 +1057,7 @@ public: void append(const RTLIL::SigSpec &signal); void append_bit(const RTLIL::SigBit &bit); - void extend(int width, bool is_signed = false); + void extend_xx(int width, bool is_signed = false); void extend_u0(int width, bool is_signed = false); RTLIL::SigSpec repeat(int num) const; |