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author | Clifford Wolf <clifford@clifford.at> | 2017-07-28 17:37:09 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2017-07-28 17:39:49 +0200 |
commit | d4b9602cbdf8ee952b396381dfc8c7ddd8f735db (patch) | |
tree | 8f626920c7414c7fe6a8d81d6d6200b05cfe2bbf /kernel | |
parent | 4cf890dac121dc977fc4507168b48e47aecf5c46 (diff) | |
download | yosys-d4b9602cbdf8ee952b396381dfc8c7ddd8f735db.tar.gz yosys-d4b9602cbdf8ee952b396381dfc8c7ddd8f735db.tar.bz2 yosys-d4b9602cbdf8ee952b396381dfc8c7ddd8f735db.zip |
Add minimal support for PSL in VHDL via Verific
Diffstat (limited to 'kernel')
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