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| author | whitequark <whitequark@whitequark.org> | 2021-02-04 09:57:28 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-02-04 09:57:28 +0000 |
| commit | baf1875307f1608762169d3037ba005da88b201e (patch) | |
| tree | 44b84ab2ef42251cdc916a417e105c3f172c2a19 /kernel | |
| parent | afcc31ceba35d33fc11f9e1592956bb4112ca0e3 (diff) | |
| parent | fe74b0cd95267bc78953236311382653a6db7f60 (diff) | |
| download | yosys-baf1875307f1608762169d3037ba005da88b201e.tar.gz yosys-baf1875307f1608762169d3037ba005da88b201e.tar.bz2 yosys-baf1875307f1608762169d3037ba005da88b201e.zip | |
Merge pull request #2529 from zachjs/unnamed-genblk
verilog: significant block scoping improvements
Diffstat (limited to 'kernel')
| -rw-r--r-- | kernel/rtlil.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index cd966b815..4dad3c428 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -334,6 +334,10 @@ namespace RTLIL return compare(size()-len, len, suffix) == 0; } + bool contains(const char* str) const { + return strstr(c_str(), str); + } + size_t size() const { return strlen(c_str()); } |