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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-13 09:49:15 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-13 09:49:15 -0700 |
| commit | 95e80809a5801743fabb2836fa25f3c3732a9a24 (patch) | |
| tree | e0ba8897072f7ffe7fa9bf3ac6a958efbc5c83bc /kernel | |
| parent | c487a8ff25a89506423e868ff3b4345bc36a8e00 (diff) | |
| download | yosys-95e80809a5801743fabb2836fa25f3c3732a9a24.tar.gz yosys-95e80809a5801743fabb2836fa25f3c3732a9a24.tar.bz2 yosys-95e80809a5801743fabb2836fa25f3c3732a9a24.zip | |
Revert "SigSet<Cell*> to use stable compare class"
This reverts commit 4ea34aaacdf6f76e11a83d5eb2a53ba7e75f7c11.
Diffstat (limited to 'kernel')
| -rw-r--r-- | kernel/consteval.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/kernel/consteval.h b/kernel/consteval.h index c1c0c45cc..7a83d28e7 100644 --- a/kernel/consteval.h +++ b/kernel/consteval.h @@ -33,7 +33,7 @@ struct ConstEval SigMap assign_map; SigMap values_map; SigPool stop_signals; - SigSet<RTLIL::Cell*, RTLIL::sort_by_name_id<RTLIL::Cell>> sig2driver; + SigSet<RTLIL::Cell*> sig2driver; std::set<RTLIL::Cell*> busy; std::vector<SigMap> stack; RTLIL::State defaultval; |