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| author | Clifford Wolf <clifford@clifford.at> | 2014-12-21 16:52:05 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-12-21 16:52:05 +0100 |
| commit | 76fa5274927e8f960060938e10a042d85268a6ac (patch) | |
| tree | 26478057a9c400af559a1d918227541961ccb75d /kernel | |
| parent | 25844b5683ab0d9a8ba5f4ee01bb5a601a1c8d24 (diff) | |
| download | yosys-76fa5274927e8f960060938e10a042d85268a6ac.tar.gz yosys-76fa5274927e8f960060938e10a042d85268a6ac.tar.bz2 yosys-76fa5274927e8f960060938e10a042d85268a6ac.zip | |
Added support for multiple clock domains to "abc" pass
Diffstat (limited to 'kernel')
| -rw-r--r-- | kernel/rtlil.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 19996c8fc..efb8e833a 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -1017,6 +1017,7 @@ public: inline const std::vector<RTLIL::SigBit> &bits() const { inline_unpack(); return bits_; } inline int size() const { return width_; } + inline bool empty() const { return width_ == 0; } inline RTLIL::SigBit &operator[](int index) { inline_unpack(); return bits_.at(index); } inline const RTLIL::SigBit &operator[](int index) const { inline_unpack(); return bits_.at(index); } |