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| author | Clifford Wolf <clifford@clifford.at> | 2015-10-24 19:09:45 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-10-24 19:09:45 +0200 |
| commit | 6fe48cf41ef0b0158879add600c7a426a5c4a762 (patch) | |
| tree | c9de66f5fe0848219a23492e89d3ff11bd6b63ed /kernel | |
| parent | 2a0f577f839bc43a5045ddf5a2b580bba8cabeab (diff) | |
| download | yosys-6fe48cf41ef0b0158879add600c7a426a5c4a762.tar.gz yosys-6fe48cf41ef0b0158879add600c7a426a5c4a762.tar.bz2 yosys-6fe48cf41ef0b0158879add600c7a426a5c4a762.zip | |
equiv_purge bugfix, using SigChunk in Yosys namespace
Diffstat (limited to 'kernel')
| -rw-r--r-- | kernel/yosys.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/kernel/yosys.h b/kernel/yosys.h index 6aacd4d54..af849fca8 100644 --- a/kernel/yosys.h +++ b/kernel/yosys.h @@ -169,6 +169,7 @@ namespace RTLIL { struct IdString; struct Const; struct SigBit; + struct SigChunk; struct SigSpec; struct Wire; struct Cell; @@ -184,6 +185,7 @@ namespace AST { using RTLIL::IdString; using RTLIL::Const; using RTLIL::SigBit; +using RTLIL::SigChunk; using RTLIL::SigSpec; using RTLIL::Wire; using RTLIL::Cell; |