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author | Marcelina KoĆcielnicka <mwk@0x04.net> | 2022-06-13 16:53:29 +0200 |
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committer | Marcelina KoĆcielnicka <mwk@0x04.net> | 2022-06-13 19:23:55 +0200 |
commit | 6b7efe12b79d4ed68af6a31f124213e101edbbb1 (patch) | |
tree | 7f5478580e5bd49689a5c3a5fc1be8eb03f7983d /kernel | |
parent | 3eaa9e38e0a8996b088f5ae3d751989d5e578fa9 (diff) | |
download | yosys-6b7efe12b79d4ed68af6a31f124213e101edbbb1.tar.gz yosys-6b7efe12b79d4ed68af6a31f124213e101edbbb1.tar.bz2 yosys-6b7efe12b79d4ed68af6a31f124213e101edbbb1.zip |
Add a check for packed memory MEMID uniqueness
Diffstat (limited to 'kernel')
-rw-r--r-- | kernel/rtlil.cc | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 8346b56e0..dc4ea9a78 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1842,6 +1842,8 @@ void RTLIL::Module::check() log_assert(!it2.first.empty()); } + pool<IdString> packed_memids; + for (auto &it : cells_) { log_assert(this == it.second->module); log_assert(it.first == it.second->name); @@ -1857,6 +1859,14 @@ void RTLIL::Module::check() log_assert(!it2.first.empty()); InternalCellChecker checker(this, it.second); checker.check(); + if (it.second->has_memid()) { + log_assert(memories.count(it.second->parameters.at(ID::MEMID).decode_string())); + } else if (it.second->is_mem_cell()) { + IdString memid = it.second->parameters.at(ID::MEMID).decode_string(); + log_assert(!memories.count(memid)); + log_assert(!packed_memids.count(memid)); + packed_memids.insert(memid); + } } for (auto &it : processes) { |