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| author | Clifford Wolf <clifford@clifford.at> | 2019-03-23 16:02:01 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-03-23 16:02:01 +0100 |
| commit | 2cf71e2a7b053505ed80ad18c0e506c5f090b595 (patch) | |
| tree | f53eeea0713e6e052eec79c588f19a948c073b41 /kernel | |
| parent | a440f82586eda461ae2a90cba7a14d7078c41f37 (diff) | |
| parent | 1eff8be8f018bd6b94efd14a959d6f1807dd056d (diff) | |
| download | yosys-2cf71e2a7b053505ed80ad18c0e506c5f090b595.tar.gz yosys-2cf71e2a7b053505ed80ad18c0e506c5f090b595.tar.bz2 yosys-2cf71e2a7b053505ed80ad18c0e506c5f090b595.zip | |
Merge pull request #893 from YosysHQ/clifford/btormeminit
Memory init support in write_btor
Diffstat (limited to 'kernel')
| -rw-r--r-- | kernel/rtlil.cc | 2 | ||||
| -rw-r--r-- | kernel/rtlil.h | 8 |
2 files changed, 9 insertions, 1 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index d0fa88890..b3214579d 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -3237,7 +3237,7 @@ void RTLIL::SigSpec::extend_u0(int width, bool is_signed) remove(width, width_ - width); if (width_ < width) { - RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::S0; + RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::Sx; if (!is_signed) padding = RTLIL::State::S0; while (width_ < width) diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 01323d112..52496e702 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -546,6 +546,14 @@ struct RTLIL::Const return ret; } + void extu(int width) { + bits.resize(width, RTLIL::State::S0); + } + + void exts(int width) { + bits.resize(width, bits.empty() ? RTLIL::State::Sx : bits.back()); + } + inline unsigned int hash() const { unsigned int h = mkhash_init; for (auto b : bits) |