Added "dump" command (part ilang backend)

2 files changed, 16 insertions, 16 deletions

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index b0dcfe428..2c255285f 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -101,7 +101,7 @@ std::string RTLIL::Const::as_string() const
 	return ret;
 }
 
-bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name)
+bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name) const
 {
 	if (full_selection)
 		return true;
@@ -112,7 +112,7 @@ bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name)
 	return false;
 }
 
-bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name)
+bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name) const
 {
 	if (full_selection)
 		return true;
@@ -121,14 +121,14 @@ bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name)
 	return false;
 }
 
-bool RTLIL::Selection::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name)
+bool RTLIL::Selection::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
 {
 	if (full_selection)
 		return true;
 	if (selected_modules.count(mod_name) > 0)
 		return true;
 	if (selected_members.count(mod_name) > 0)
-		if (selected_members[mod_name].count(memb_name) > 0)
+		if (selected_members.at(mod_name).count(memb_name) > 0)
 			return true;
 	return false;
 }
@@ -217,7 +217,7 @@ void RTLIL::Design::optimize()
 		it.second.optimize(this);
 }
 
-bool RTLIL::Design::selected_module(RTLIL::IdString mod_name)
+bool RTLIL::Design::selected_module(RTLIL::IdString mod_name) const
 {
 	if (!selected_active_module.empty() && mod_name != selected_active_module)
 		return false;
@@ -226,7 +226,7 @@ bool RTLIL::Design::selected_module(RTLIL::IdString mod_name)
 	return selection_stack.back().selected_module(mod_name);
 }
 
-bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name)
+bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name) const
 {
 	if (!selected_active_module.empty() && mod_name != selected_active_module)
 		return false;
@@ -235,7 +235,7 @@ bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name)
 	return selection_stack.back().selected_whole_module(mod_name);
 }
 
-bool RTLIL::Design::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name)
+bool RTLIL::Design::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
 {
 	if (!selected_active_module.empty() && mod_name != selected_active_module)
 		return false;
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index fe88182fa..b15082889 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -189,9 +189,9 @@ struct RTLIL::Selection {
 	std::set<RTLIL::IdString> selected_modules;
 	std::map<RTLIL::IdString, std::set<RTLIL::IdString>> selected_members;
 	Selection(bool full = true) : full_selection(full) { }
-	bool selected_module(RTLIL::IdString mod_name);
-	bool selected_whole_module(RTLIL::IdString mod_name);
-	bool selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name);
+	bool selected_module(RTLIL::IdString mod_name) const;
+	bool selected_whole_module(RTLIL::IdString mod_name) const;
+	bool selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const;
 	void optimize(RTLIL::Design *design);
 };
 
@@ -203,20 +203,20 @@ struct RTLIL::Design {
 	~Design();
 	void check();
 	void optimize();
-	bool selected_module(RTLIL::IdString mod_name);
-	bool selected_whole_module(RTLIL::IdString mod_name);
-	bool selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name);
-	template<typename T1> bool selected(T1 *module) {
+	bool selected_module(RTLIL::IdString mod_name) const;
+	bool selected_whole_module(RTLIL::IdString mod_name) const;
+	bool selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const;
+	template<typename T1> bool selected(T1 *module) const {
 		return selected_module(module->name);
 	}
-	template<typename T1, typename T2> bool selected(T1 *module, T2 *member) {
+	template<typename T1, typename T2> bool selected(T1 *module, T2 *member) const {
 		return selected_member(module->name, member->name);
 	}
 	template<typename T1, typename T2> void select(T1 *module, T2 *member) {
 		if (selection_stack.size() > 0) {
 			RTLIL::Selection &sel = selection_stack.back();
 			if (!sel.full_selection && sel.selected_modules.count(module->name) == 0)
-				sel.selected_members[module->name].insert(member->name);
+				sel.selected_members.at(module->name).insert(member->name);
 		}
 	}
 };