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authorAhmed Irfan <ahmedirfan1983@gmail.com>2014-01-03 16:54:32 +0100
committerAhmed Irfan <ahmedirfan1983@gmail.com>2014-01-03 16:54:32 +0100
commit09f16c9d0c1f0b8aec4a376449c831fa98a4e985 (patch)
tree05f4f6540424fc52405128dced69c02614efed77 /kernel
parent06482c046bcab4e2b9603f8954ce0f2fd501a73b (diff)
parent60fbca9970e1b92d61642b86d2a3170b5b33ad6f (diff)
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splitnet -driver feature
Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor
Diffstat (limited to 'kernel')
-rw-r--r--kernel/rtlil.cc7
-rw-r--r--kernel/rtlil.h1
2 files changed, 8 insertions, 0 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 1311f31cc..661525735 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -1024,6 +1024,13 @@ void RTLIL::SigSpec::optimize()
check();
}
+RTLIL::SigSpec RTLIL::SigSpec::optimized() const
+{
+ RTLIL::SigSpec ret = *this;
+ ret.optimize();
+ return ret;
+}
+
bool RTLIL::SigChunk::compare(const RTLIL::SigChunk &a, const RTLIL::SigChunk &b)
{
if (a.wire != b.wire) {
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 8e3b78eef..504fdbbdc 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -373,6 +373,7 @@ struct RTLIL::SigSpec {
SigSpec(std::vector<RTLIL::SigBit> bits);
void expand();
void optimize();
+ RTLIL::SigSpec optimized() const;
void sort();
void sort_and_unify();
void replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with);