Merge branch 'eddie/fix_retime' into xc7srl

2 files changed, 25 insertions, 0 deletions

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index b3214579d..9ae20a317 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -641,6 +641,30 @@ RTLIL::Module::~Module()
 		delete it->second;
 }
 
+void RTLIL::Module::makeblackbox()
+{
+	pool<RTLIL::Wire*> delwires;
+
+	for (auto it = wires_.begin(); it != wires_.end(); ++it)
+		if (!it->second->port_input && !it->second->port_output)
+			delwires.insert(it->second);
+
+	for (auto it = memories.begin(); it != memories.end(); ++it)
+		delete it->second;
+	memories.clear();
+
+	for (auto it = cells_.begin(); it != cells_.end(); ++it)
+		delete it->second;
+	cells_.clear();
+
+	for (auto it = processes.begin(); it != processes.end(); ++it)
+		delete it->second;
+	processes.clear();
+
+	remove(delwires);
+	set_bool_attribute("\\blackbox");
+}
+
 void RTLIL::Module::reprocess_module(RTLIL::Design *, dict<RTLIL::IdString, RTLIL::Module *>)
 {
 	log_error("Cannot reprocess_module module `%s' !\n", id2cstr(name));
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 52496e702..fb045bc72 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -976,6 +976,7 @@ public:
 	virtual void sort();
 	virtual void check();
 	virtual void optimize();
+	virtual void makeblackbox();
 
 	void connect(const RTLIL::SigSig &conn);
 	void connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs);