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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-15 16:23:12 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-15 16:23:12 -0700 |
| commit | b29f26f6c7d880b9a446f6eacfa988c2018a1e30 (patch) | |
| tree | 1ce75cc63a4d9f24931501451a6b8a8ac204d7b5 /kernel/rtlil.h | |
| parent | 5f00d335d4861fc03dd7b6cee68fd79505bd3d41 (diff) | |
| download | yosys-b29f26f6c7d880b9a446f6eacfa988c2018a1e30.tar.gz yosys-b29f26f6c7d880b9a446f6eacfa988c2018a1e30.tar.bz2 yosys-b29f26f6c7d880b9a446f6eacfa988c2018a1e30.zip | |
SigSpec::extend_u0() to return *this
Diffstat (limited to 'kernel/rtlil.h')
| -rw-r--r-- | kernel/rtlil.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 82cbfaf28..8d88cc97c 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -776,7 +776,7 @@ public: void append(const RTLIL::SigSpec &signal); void append_bit(const RTLIL::SigBit &bit); - void extend_u0(int width, bool is_signed = false); + RTLIL::SigSpec& extend_u0(int width, bool is_signed = false); RTLIL::SigSpec repeat(int num) const; |