aboutsummaryrefslogtreecommitdiffstats
path: root/kernel/mem.cc
diff options
context:
space:
mode:
authorMarcelina Koƛcielnicka <mwk@0x04.net>2021-05-22 16:10:18 +0200
committerMarcelina Koƛcielnicka <mwk@0x04.net>2021-05-22 21:42:53 +0200
commitff9e0394b86f701db17ceda48bf8075ce8ac597d (patch)
tree993c3561ab40550dab42dff915dc8f206d802bec /kernel/mem.cc
parent8c734e07b87974fc4931d41b37b459d2c664e1bf (diff)
downloadyosys-ff9e0394b86f701db17ceda48bf8075ce8ac597d.tar.gz
yosys-ff9e0394b86f701db17ceda48bf8075ce8ac597d.tar.bz2
yosys-ff9e0394b86f701db17ceda48bf8075ce8ac597d.zip
kernel/mem: defer port removal to emit()
Diffstat (limited to 'kernel/mem.cc')
-rw-r--r--kernel/mem.cc48
1 files changed, 34 insertions, 14 deletions
diff --git a/kernel/mem.cc b/kernel/mem.cc
index 0301a913c..9d68dbbb7 100644
--- a/kernel/mem.cc
+++ b/kernel/mem.cc
@@ -52,6 +52,40 @@ void Mem::remove() {
}
void Mem::emit() {
+ std::vector<int> rd_left;
+ for (int i = 0; i < GetSize(rd_ports); i++) {
+ auto &port = rd_ports[i];
+ if (port.removed) {
+ if (port.cell) {
+ module->remove(port.cell);
+ }
+ } else {
+ rd_left.push_back(i);
+ }
+ }
+ std::vector<int> wr_left;
+ for (int i = 0; i < GetSize(wr_ports); i++) {
+ auto &port = wr_ports[i];
+ if (port.removed) {
+ if (port.cell) {
+ module->remove(port.cell);
+ }
+ } else {
+ wr_left.push_back(i);
+ }
+ }
+ for (int i = 0; i < GetSize(rd_left); i++)
+ if (i != rd_left[i])
+ std::swap(rd_ports[i], rd_ports[rd_left[i]]);
+ rd_ports.resize(GetSize(rd_left));
+ for (int i = 0; i < GetSize(wr_left); i++)
+ if (i != wr_left[i])
+ std::swap(wr_ports[i], wr_ports[wr_left[i]]);
+ wr_ports.resize(GetSize(wr_left));
+
+ // for future: handle transparency mask here
+ // for future: handle priority mask here
+
if (packed) {
if (mem) {
module->memories.erase(mem->name);
@@ -205,20 +239,6 @@ void Mem::emit() {
}
}
-void Mem::remove_wr_port(int idx) {
- if (wr_ports[idx].cell) {
- module->remove(wr_ports[idx].cell);
- }
- wr_ports.erase(wr_ports.begin() + idx);
-}
-
-void Mem::remove_rd_port(int idx) {
- if (rd_ports[idx].cell) {
- module->remove(rd_ports[idx].cell);
- }
- rd_ports.erase(rd_ports.begin() + idx);
-}
-
void Mem::clear_inits() {
for (auto &init : inits)
if (init.cell)