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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2021-05-25 22:39:50 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-05-25 23:42:31 +0200 |
| commit | d99fce3bc77a42563e1e270172e08ec25d58c7ab (patch) | |
| tree | 6e7f5cd961356735acfd5fe987a9f4ae3b88b5c6 /kernel/mem.cc | |
| parent | 18806f1ef653f29654533ee47fd8a1b0cf1d645a (diff) | |
| download | yosys-d99fce3bc77a42563e1e270172e08ec25d58c7ab.tar.gz yosys-d99fce3bc77a42563e1e270172e08ec25d58c7ab.tar.bz2 yosys-d99fce3bc77a42563e1e270172e08ec25d58c7ab.zip | |
mem/extract_rdff: Fix "no FF made" edge case.
When converting a sync transparent read port with const address to async
read port, nothing at all needs to be done other than clk_enable change,
and thus we have no FF cell to return. Handle this case correctly in
the helper and in its users.
Diffstat (limited to 'kernel/mem.cc')
| -rw-r--r-- | kernel/mem.cc | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/kernel/mem.cc b/kernel/mem.cc index 5d0a01dd2..fe88be5d7 100644 --- a/kernel/mem.cc +++ b/kernel/mem.cc @@ -579,7 +579,8 @@ Cell *Mem::extract_rdff(int idx, FfInitVals *initvals) { if (port.addr[i].wire) width++; - if (width) { + if (width) + { SigSpec sig_q = module->addWire(stringf("$%s$rdreg[%d]$q", memid.c_str(), idx), width); SigSpec sig_d; @@ -591,6 +592,8 @@ Cell *Mem::extract_rdff(int idx, FfInitVals *initvals) { } c = module->addDff(stringf("$%s$rdreg[%d]", memid.c_str(), idx), port.clk, sig_d, sig_q, port.clk_polarity); + } else { + c = nullptr; } } else |