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author | Clifford Wolf <clifford@clifford.at> | 2019-08-10 12:24:16 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2019-08-11 11:39:46 +0200 |
commit | 390bf459fbd766d4b1f9d16c6e10d665b43369d5 (patch) | |
tree | a5ed298e5fe5604d4ef70bc055b19009f1ceb634 /kernel/macc.h | |
parent | 8222c5735e3b31fc2a7507abe607bb5aa9f863de (diff) | |
download | yosys-390bf459fbd766d4b1f9d16c6e10d665b43369d5.tar.gz yosys-390bf459fbd766d4b1f9d16c6e10d665b43369d5.tar.bz2 yosys-390bf459fbd766d4b1f9d16c6e10d665b43369d5.zip |
Use ID() in kernel/*, add simple ID:: hack (to be improved upon later)
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'kernel/macc.h')
-rw-r--r-- | kernel/macc.h | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/kernel/macc.h b/kernel/macc.h index c7595ebc1..e07e7e01a 100644 --- a/kernel/macc.h +++ b/kernel/macc.h @@ -99,16 +99,16 @@ struct Macc void from_cell(RTLIL::Cell *cell) { - RTLIL::SigSpec port_a = cell->getPort("\\A"); + RTLIL::SigSpec port_a = cell->getPort(ID(A)); ports.clear(); - bit_ports = cell->getPort("\\B"); + bit_ports = cell->getPort(ID(B)); - std::vector<RTLIL::State> config_bits = cell->getParam("\\CONFIG").bits; + std::vector<RTLIL::State> config_bits = cell->getParam(ID(CONFIG)).bits; int config_cursor = 0; #ifndef NDEBUG - int config_width = cell->getParam("\\CONFIG_WIDTH").as_int(); + int config_width = cell->getParam(ID(CONFIG_WIDTH)).as_int(); log_assert(GetSize(config_bits) >= config_width); #endif @@ -191,12 +191,12 @@ struct Macc port_a.append(port.in_b); } - cell->setPort("\\A", port_a); - cell->setPort("\\B", bit_ports); - cell->setParam("\\CONFIG", config_bits); - cell->setParam("\\CONFIG_WIDTH", GetSize(config_bits)); - cell->setParam("\\A_WIDTH", GetSize(port_a)); - cell->setParam("\\B_WIDTH", GetSize(bit_ports)); + cell->setPort(ID(A), port_a); + cell->setPort(ID(B), bit_ports); + cell->setParam(ID(CONFIG), config_bits); + cell->setParam(ID(CONFIG_WIDTH), GetSize(config_bits)); + cell->setParam(ID(A_WIDTH), GetSize(port_a)); + cell->setParam(ID(B_WIDTH), GetSize(bit_ports)); } bool eval(RTLIL::Const &result) const |