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| author | Miodrag Milanović <mmicko@gmail.com> | 2022-03-17 17:15:36 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-03-17 17:15:36 +0100 |
| commit | 0c5279b73da7fcb4d92fc2ddd9d79a2a29254096 (patch) | |
| tree | b3961d2ea83b0bacfae2c97b3528120fa8ae606d /kernel/fstdata.cc | |
| parent | e1d4863a19150d6e50b3c4d6725a7f867c68d46a (diff) | |
| parent | 1f3423cd7d72d764217378200d7d1bd5ab721112 (diff) | |
| download | yosys-0c5279b73da7fcb4d92fc2ddd9d79a2a29254096.tar.gz yosys-0c5279b73da7fcb4d92fc2ddd9d79a2a29254096.tar.bz2 yosys-0c5279b73da7fcb4d92fc2ddd9d79a2a29254096.zip | |
Merge pull request #3236 from YosysHQ/micko/tb_initial
Recognize registers and set initial state for them in tb
Diffstat (limited to 'kernel/fstdata.cc')
| -rw-r--r-- | kernel/fstdata.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/kernel/fstdata.cc b/kernel/fstdata.cc index 587678ce3..82f8ff1df 100644 --- a/kernel/fstdata.cc +++ b/kernel/fstdata.cc @@ -113,6 +113,7 @@ void FstData::extractVarNames() FstVar var; var.id = h->u.var.handle; var.is_alias = h->u.var.is_alias; + var.is_reg = (fstVarType)h->u.var.typ == FST_VT_VCD_REG; var.name = remove_spaces(h->u.var.name); var.scope = scopes.back(); var.width = h->u.var.length; |