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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2021-03-15 15:38:45 +0100 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-05-23 14:46:59 +0200 |
| commit | 1eea06bcc0750de02a460f3e949df2f68f800382 (patch) | |
| tree | 87986f2359f7ab5e63a454efe894a34e98845726 /kernel/ffinit.h | |
| parent | a23d9409e7d04fcfa31a139d0cf6169be4c46fca (diff) | |
| download | yosys-1eea06bcc0750de02a460f3e949df2f68f800382.tar.gz yosys-1eea06bcc0750de02a460f3e949df2f68f800382.tar.bz2 yosys-1eea06bcc0750de02a460f3e949df2f68f800382.zip | |
Add new helper class for merging FFs into cells, use for memory_dff.
Fixes #1854.
Diffstat (limited to 'kernel/ffinit.h')
| -rw-r--r-- | kernel/ffinit.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/kernel/ffinit.h b/kernel/ffinit.h index 025b0c862..9d33ac572 100644 --- a/kernel/ffinit.h +++ b/kernel/ffinit.h @@ -28,7 +28,6 @@ YOSYS_NAMESPACE_BEGIN struct FfInitVals { const SigMap *sigmap; - RTLIL::Module *module; dict<SigBit, std::pair<State,SigBit>> initbits; void set(const SigMap *sigmap_, RTLIL::Module *module) |