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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2022-05-13 16:59:52 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2022-05-13 23:02:30 +0200 |
| commit | 2858bb03cd1e3417a5a8c4ebca10877b4fd64bfa (patch) | |
| tree | abc11e2fc86a7e8072005db252417a90cbd0a135 /kernel/ff.cc | |
| parent | f56a3bd48f39138febc1de960982844f95e5c54f (diff) | |
| download | yosys-2858bb03cd1e3417a5a8c4ebca10877b4fd64bfa.tar.gz yosys-2858bb03cd1e3417a5a8c4ebca10877b4fd64bfa.tar.bz2 yosys-2858bb03cd1e3417a5a8c4ebca10877b4fd64bfa.zip | |
Add opt_ffinv pass.
Diffstat (limited to 'kernel/ff.cc')
| -rw-r--r-- | kernel/ff.cc | 13 |
1 files changed, 10 insertions, 3 deletions
diff --git a/kernel/ff.cc b/kernel/ff.cc index c43482bd2..b0f1a924f 100644 --- a/kernel/ff.cc +++ b/kernel/ff.cc @@ -669,14 +669,12 @@ namespace { } } -void FfData::flip_bits(const pool<int> &bits) { +void FfData::flip_rst_bits(const pool<int> &bits) { if (!bits.size()) return; remove_init(); - Wire *new_q = module->addWire(NEW_ID, width); - for (auto bit: bits) { if (has_arst) val_arst[bit] = invert(val_arst[bit]); @@ -684,6 +682,15 @@ void FfData::flip_bits(const pool<int> &bits) { val_srst[bit] = invert(val_srst[bit]); val_init[bit] = invert(val_init[bit]); } +} + +void FfData::flip_bits(const pool<int> &bits) { + if (!bits.size()) + return; + + flip_rst_bits(bits); + + Wire *new_q = module->addWire(NEW_ID, width); if (has_sr && cell) { log_warning("Flipping D/Q/init and inserting priority fixup to legalize %s.%s [%s].\n", log_id(module->name), log_id(cell->name), log_id(cell->type)); |